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| 4-bit single-chip microcomputer description the m pd75216a is a microcomputer with a cpu capable of 1-, 4-, and 8-bit data processing, rom, ram, i/o ports, a fluorescent display tube controller/driver, a watch timer, a timer/pulse generator capable of outputting 14-bit pwm, a serial interface and a vectored interrupt function integrated on a single-chip. the m pd75216a is a product with the rom capacity and the number of display segments extended for the m pd75208. it uses the vcr, ecr and cd fluorescent display tubes as display devices and is most suitable for applications requiring the timer/watch function and high-speed interrupt servicing. it can help to provide the unit with many functions and to decrease performance costs. functions are described in detail in the following users manual. be sure to read when carrying out design work. m pd75216a users manual: iem-988 features architecture equal to that of an 8-bit microcomputer high-speed operation : minimum instruction execution time : 0.95 m s (when operated at 4.19 mhz) instruction execution time variable function realizing a wide range of operating voltages on-chip large-capacity program memory : 16k bytes watch operation with an ultra low current consumption : 5 m a typ. (at the 3 v operation) on-chip programmable fluorescent display tube controller/driver timer function : 4 ch ? 14-bit pwm output capability with the voltage synthesizer type electronic tuner ? buzzer output capability interrupt function with importance attached to applications ? for power-off detection ? for remote controlled reception product with an on-chip prom : m pd75p216a, m pd75p218 (on-chip eprom : wqfn package) application field vcr, cd player, ecr, etc. m pd75216a mos integrated circuit data sheet the information in this document is subject to change without notice. the mark h shows major revised points. ? nec corporation 1990 document no. ic-1999c (o. d. no. ic-7177d) date published february 1994 p printed in japan www.datasheet.co.kr datasheet pdf - http://www..net/
2 m pd75216a ordering information ordering code package quality grade m pD75216ACW- 64-pin plastic shrink dip (750 mil) standard m pd75216agf- -3be 64-pin plastic qfp (14 20 mm) standard remarks is a rom code number. please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. www.datasheet.co.kr datasheet pdf - http://www..net/ 3 m pd75216a instruction execution time on-chip memory rom ram general register input/output port fip dual-function pin included fip dedicated pin excluded fip controller/driver timer serial interface vectored interrupt test input system clock oscillator standby function mask option operating temperature range operating voltage package ? 0.95, 1.91, 15.3 m s (main system clock : 4.19 mhz operation) ? 122 m s (subsystem clock : 32.768 khz operation) 16256 8 bits 512 4 bits ? 4-bit manipulation : 8 4 banks ? 8-bit manipulation : 4 4 banks 33 8 cmos input pin 20 cmos input/output pins ? direct led drive capability : 8 ? on-chip pull-down resistor by mask option capability : 4 1 cmos output pin pwm/pulse output 4 p-ch open-drain, ? led drive capability high-voltage, ? on-chip pull-down resistor by mask option capability high-current output pin ? no. of segments : 9 to 16 segments ? no. of digits : 9 to 16 digits ? dimmer function : 8 levels ? on-chip pull-down resistor by mask option capability ? key scan interrupt generation 4 channels ? timer/pulse generator : 14-bit pwm output enabled ? watch timer : buzzer output enabled ? timer/event counter ? basic interval timer : watchdog timer application capability ? msb start/lsb start switchable ? serial bus configuration capability external : 3, internal : 5 external : 1, internal : 1 ? ceramic/crystal oscillator for main system clock oscillation : 4.194304 mhz standard ? crystal oscillator for subsystem clock oscillation : 32.768 khz standard stop/halt mode ? power-on reset, power-on flag ? high withstand voltage port : pull-down resistor or open-drain output ? port 6 : pull-down resistor C40 to +85 c 2.7 to 6.0 v (standby data hold : 2.0 to 6.0 v) ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 20 mm) item function ? ? ? ? ? ? ? list of functions www.datasheet.co.kr datasheet pdf - http://www..net/ 4 m pd75216a contents 1. pin configuration (top view) ......................................................................................................... 6 2. block diagram ...................................................................................................................................... 8 3. pin functions ........................................................................................................................................ 9 3.1 port pins ............................................................................................................................................................. 9 3.2 non-port pins .................................................................................................................................................. 10 3.3 pin input/output circuit list .................................................................................................................... 11 3.4 unused pins treatment .............................................................................................................................. 12 3.5 p00/int4 pin and reset pin operating precautions ......................................................................... 13 3.6 xt1, xt2 and p50 pin operating precautions ..................................................................................... 13 4. memory configuration ................................................................................................................... 14 5. peripheral hardware functions ................................................................................................. 17 5.1 ports .................................................................................................................................................................... 17 5.2 clock generator ............................................................................................................................................ 18 5.3 basic interval timer ..................................................................................................................................... 19 5.4 watch timer ...................................................................................................................................................... 20 5.5 timer/event counter ................................................................................................................................... 21 5.6 timer/pulse generator ............................................................................................................................... 22 5.7 serial interface ............................................................................................................................................. 23 5.8 fip controller /driver ................................................................................................................................ 25 5.9 power-on flag (mask option) ................................................................................................................... 27 6. interrupt functions ......................................................................................................................... 28 7. standby functions ............................................................................................................................ 30 8. reset functions .................................................................................................................................. 31 9. instruction set ................................................................................................................................... 34 10. mask option selection .................................................................................................................... 43 11. application block diagram ............................................................................................................ 44 11.1 vcr timer tuner ............................................................................................................................................. 44 11.2 cd player .......................................................................................................................................................... 45 11.3 ecr ....................................................................................................................................................................... 45 12. electrical specifications ............................................................................................................... 46 13. characteristic curves .................................................................................................................... 59 14. package information ....................................................................................................................... 63 www.datasheet.co.kr datasheet pdf - http://www..net/ 5 m pd75216a 15. recommended soldering conditions ........................................................................................ 66 appendix a. list of m pd75216a series product functions ........................................................ 67 appendix b. development tools ......................................................................................................... 69 appendix c. related documents ......................................................................................................... 70 www.datasheet.co.kr datasheet pdf - http://www..net/ 6 m pd75216a s3 s2 s1 s0 p00/int4 p01/sck p02/so p03/si p10/int0 p11/int1 p12/int2 p13/ti0 p20 p21 p22 p23/buz p30 p31 p32 p33 p60 p61 p62 p63 p40 p41 p42 p43 ppo x1 x2 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v dd s4 s5 s6 s7 s8 s9 v pre v load t15/s10 t14/s11 t13/s12/ph0 t12/s13/ph1 t11/s14/ph2 t10/s15/ph3 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 reset p53 p52 p51 p50 xt2 xt1 p41 p42 p43 ppo x1 x2 v ss xt1 xt2 p50 p51 p52 p53 32 31 30 29 28 27 26 25 24 23 22 21 20 p01/sck p00/int4 s0 s1 s2 s3 v dd s4 s5 s6 s7 s8 s9 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 52 53 54 55 56 57 58 59 60 61 62 63 64 p40 p63 p62 p61 p60 p33 p32 p31 p30 p23/buz p22 p21 p20 p13/ti0 p12/int2 p11/int1 p10/int0 p03/si p02/so reset t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 v pre t10/s15/ph3 t11/s14/ph2 t12/s13/ph1 t13/s12/ph0 t14/s11 t15/s10 v load 1. pin configuration (top view) m pD75216ACW- m pd75216agf- -3be www.datasheet.co.kr datasheet pdf - http://www..net/ 7 m pd75216a pin name p00-p03 : port 0 p10-p13 : port 1 p20-p23 : port 2 p30-p33 : port 3 p40-p43 : port 4 p50-p53 : port 5 p60-p63 : port 6 ph0-ph3 : port h t0-t15 : digit output 0-15 s0-s15 : segment output 0-15 ppo : pulse output buz : fixed frequency output sck : serial clock so : serial output si : serial input int0, int1, int4 : external vectored interrupt 0, 1, 4 int2 : external test input 2 ti0 : timer input 0 x1, x2 : main system clock oscillation 1, 2 xt1, xt2 : subsystem clock oscillation 1, 2 reset : reset input v load , v pre : fip driver power supply pin www.datasheet.co.kr datasheet pdf - http://www..net/ 8 m pd75216a 2. block diagram basic interval timer timer/event counter #0 timer/pulse generator intbt intt0 inttpg serial interface interrupt control intsio ti0/p13 ppo si/p03 so/p02 sck/p01 int0/p10 int1/p11 int2/p12 int4/p00 buz/p23 watch timer intw f x /2 n clock divider system clock generator sub main stand by control xt1 xt2 x1 x2 v dd v ss reset cpu clock f program counter(14) rom program memory 16256 8 bits decode and control ram data memory 512 4 bits general reg. bank sp(8) cy alu port0 4 p00?03 port1 4 p10?13 port2 4 p20?23 port3 4 p30?33 port4 4 p40?43 port5 4 p50?53 port6 4 p60?63 fip controller/ driver 10 t0?9 4 t10/s15/ph3? t13/s12/ph0 2 t14/s11,t15/ s10 10 s0?9 v pre v load porth 4 ph0?h3 intks www.datasheet.co.kr datasheet pdf - http://www..net/ 9 m pd75216a input input input input/ output b f g b int4 sck so si int0 int1 int2 ti0 CCC CCC CCC buz CCC CCC CCC CCC t13/s12 t12/s13 t11/s14 t10/s15 p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 to p33 p40 to p43 p50 to p53 p60 to p63 ph0 ph1 ph2 ph3 3. pin functions 3.1 port pins after reset function input/output input/output 4-bit input port (port0). input b input noise elimination function available noise elimination function available 4-bit input port (port1). 4-bit input/output port (port2). input e programmable 4-bit input/ output port (port3). input/output specifiable in 1-bit units. input/ output input e input/ output 4-bit input/output port (port4). led direct drive capability. l l input e input/ output 4-bit input/output port (port5). led direct drive capability. input e input/ output programmable 4-bit input/output port (port6). input/output specifiable in bit-wise. on-chip pull-down resistor available (mask option). suitable for key input. input v output 4-bit p-ch open-drain, high-voltage, high-current output port (porth). led direct drive capability. on-chip pull-down resistor available (mask option). i * schmitt-triggered inputs are circled. low level (with an on- chip pull- down resistor) or high impedance. dual- function pin 8-bit i/o input / output circuit type * pin name i/o www.datasheet.co.kr datasheet pdf - http://www..net/ 10 m pd75216a segment output high voltage output. static output also possible. pin name i/o after reset digit/segment output dual-function high-voltage high-current output. extra pins can be used as porth. digit output high-voltage high-current output. fip controller/ driver output pins. pull-down resistor can be incorporated in bit-wise (mask option). t0 to t9 digit/segment output dual-function high-voltage high-current output. static output also possible. t10/s15 to t13/s12 t14/s11, t15/s10 s9 output CCC ph3 to ph0 CCC low level (with an on- chip pull- down resistor) or high impedance (without a pull-down resistor) i 3.2 non-port pins * schmitt-triggered inputs are circled. b f segment high-voltage output. s0 to s8 high impedance ppo output input CCC timer/pulse generator pulse output. external event pulse input for timer/event counter. p13 serial clock input/output. ti0 sck serial data input pin or serial data input/output. serial data input or normal input. edge-detected vectored interrupt input (rising and falling edge detection). int0 int1 so si int4 input/output input input input p01 p02 p03 p00 p10 p11 edge-detected vectored interrupt input with noise elimination function (detection edge selection possible). edge-detected testable input (rising edge detection). fixed frequency output (for buzzer or system clock trimming). crystal/ceramic connect pin for main system clock oscillation. external clock input to x1 and its inverted clock input to x2. crystal connect pin for subsystem clock oscillation. external clock input to xt1 and xt2 open. int2 input input/output p12 p23 buz x1, x2 xt1 input input fip controller/driver output buffer power supply. fip controller/driver pull-down resistor connect pin. gnd potential. xt2 CCC CCC CCC system reset input (low level active). reset v pre input positive power supply. v load v dd CCC CCC CCC v ss d input b input g input b b b b input e i i input/output CCC CCC dual- function pin function input / output circuit type * www.datasheet.co.kr datasheet pdf - http://www..net/ 11 m pd75216a 3.3 pin input/output circuit list type a type b type d type e type f type g type v type i v dd p-ch n-ch in in v dd p-ch n-ch out data output disable data output disable type d in/out type a data output disable type d in/out type b data output disable type d in/out type a v dd p-ch n-ch in/out data p-ch output disable type b v dd p-ch n-ch out data v dd p-ch v load v pre cmos-specified input buffer schmitt-triggered input having hysteresis characteristics push-pull output which can be set to output high impedance (with both p-ch and n-ch set to off) input/output circuit consisting of type d push-pull output and type a input buffer pull-down resistor (mask option) pull-down resistor (mask option) input/output circuit capable of switching between push-pull output and n-ch open-drain output (with p-ch off). input/output circuit consisting of type d push-pull output and type b schmitt-triggered input www.datasheet.co.kr datasheet pdf - http://www..net/ 12 m pd75216a 3.4 unused pins treatment p00/int4 p01/sck p02/so p03/si p10/int0 to p12/int2 p13/ti0 p20 to p22 p23/buz p30 to p33 p40 to p43 p50 to p53 p60 to p63 ppo s0 to s9 t15/s10 to t14/s11 t0 to t9 t10/s15/ph3 to t13/s12/ph0 xt1 xt2 reset when there is an on- chip power-on reset circuit v load when there is no on- chip load resistor connect to v ss connect to v ss or v dd connect to v ss input state : connect to v ss or v dd ouput state : leave open leave open connect to v ss or v dd leave open connect to v dd connect to v ss or v dd recommended connection pin www.datasheet.co.kr datasheet pdf - http://www..net/ 13 m pd75216a 3.5 p00/int4 pin and reset pin operating precautions p00/int4 and reset pins have the function (especially for ic test) to test m pd75216a internal operations in addition to the functions described in sections 3.1 and 3.2. the test mode is set when a voltage larger than v dd is applied to one of these pins. if noise larger than v dd is applied in normal operation, the test mode may be set thereby adversely affecting normal operation. since there is a display output pin having a high-voltage amplitude (35 v) next to the p00/int4 and reset pins, if cables for the related signals are routed in parallel, wiring noise larger than v dd may be applied to the p00/int4 and reset pins causing errors. thus, carry out wiring so that wiring noise can be minimized, if noise still cannot be suppressed, take the measure against noise using the following external components. ? connect diode with small v f (0.3 v or less) between v dd and p00/int4, reset ? connect a capacitor between the pins and v dd . v dd v dd p00/int4, reset v dd v dd p00/int4, reset 3.6 xt1, xt2 and p50 pin operating precautions when selecting the 32.768 khz subsystem clock connected to the xt1 and xt2 pins as the watch timer source clock, the signal to be input or output to the p50 pin next to the xt2 pin must be a signal required to be switched between high and low the minimum number of times (once or less per second). if the p50 pin signal is switched frequently between high and low, a spike is generated in the xt2 pin because of capacitance coupling of the p50 and xt2 pins and the correct watch functions cannot be achieved (the watch becomes fast). if it is necessary to allow the p50 pin signal to switch between high and low, mount an external capacitor to the p50 pin as shown below. xt1 32.768 khz 0.0068 f m xt2 p50 m pd75216a www.datasheet.co.kr datasheet pdf - http://www..net/ 14 m pd75216a 4. memory configuration program memory (rom) ................................. 16256 words 8 bits ? 0000h to 0001h : vector table for writing program start address by reset ? 0002h to 000fh : vector table for writing program start address by interrupt ? 0020h to 007fh : table area to be referred to by geti instruction data memory ? data area ....................................................... 512 words 4 bits (000h to 1ffh) ? peripheral hardware area ............................ 128 words 4 bits (f80h to fffh) www.datasheet.co.kr datasheet pdf - http://www..net/ 15 m pd75216a fig. 4-1 program memory map mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe 6 intbt/int4 start address internal reset start address (most significant 6 bits)? internal reset start address (least significant 8 bits)? (most significant 6 bits) intbt/int4 start address (least significant 8 bits) int0 start address (most significant 6 bits) int0 start address (least significant 8 bits) intcsi0 start address (most significant 6 bits) intcsi0 start address (least significant 8 bits) intt0 start address (most significant 6 bits) intt0 start address (least significant 8 bits) inttpg start address (most significant 6 bits) inttpg start address (least significant 8 bits) intks start address (most significant 6 bits) intks start address (least significant 8 bits) (most significant 6 bits) (least significant 8 bits) int1 start address int1 start address geti instruction reference table 0002h 0004h 0006h 0008h 000ah 000ch 000eh 0000h 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1fffh 2000h 2fffh 3000h 3f7fh callf !faddr instruction entry address brcb !caddr instruction branch address br !addr instruction branch address call !addr instruction subroutine entry address br $ addr instruction relative branch address (-15 to -1 and +2 to +16) brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address branch destination address and subroutine entry address to be set by geti instruction address 7 rbe 0 remarks in all cases other than those listed above, branch to the address with only the lower 8 bits of the pc changed is enabled by br pcde and br pcxa instructions. www.datasheet.co.kr datasheet pdf - http://www..net/ 16 m pd75216a fig. 4-2 data memory map (32 4) 256 4 (64 4) 256 4 128 4 not incorporated f80h fffh 1ffh 1c0h 1bfh 100h 0ffh 020h 000h general register area display data memory, etc. 01fh general static ram (512 4) stack area peripheral hardware area bank 0 bank 1 bank 15 www.datasheet.co.kr datasheet pdf - http://www..net/ 17 m pd75216a 5. peripheral hardware functions 5.1 ports i/o ports have the following three functions. cmos input (port0, 1) : 8 cmos input/output (port2, 3, 4, 5, 6) : 20 p-ch open-drain, high-voltage, high-current output (porth) : 4 total 32 table 5-1 port functions remarks port name always read or test possible irrespective of the dual-function pin operating mode. always read or test possible, p10 and p11 are inputs with the noise elimination function. can be set bit-wise to the input or output mode. port 6 can incorporate a pull-down resistor as a mask option. can be set to the input or output mode in 4-bit units. ports 4 and 5 can input/output data in pairs in 8-bit units. ports 4 and 5 can directly drive leds. p-ch open-drain high-voltage, high-current output port. can drive an fip and led directly. can incorporate a pull-down resistor bit-wise as a mask option. shares the pins with si, so, sck and int4. shares the pins with int0 to int 2 and ti0. p23 shares the pin with buz. shares the pins with t10/s15 to t13/s12. operation and feature function 4-bit input port0 port1 port3 port6 4-bit input/output port2 port4 port5 porth 4-bit output www.datasheet.co.kr datasheet pdf - http://www..net/ 18 m pd75216a 5.2 clock generator the clock generator operations are determined by the processor clock control register (pcc) and the system clock control register (scc). the clock generator has two types: main system clock and subsystem clock. the instruction execution time can be changed. 0.95 m s, 1.91 m s, 15.3 m s (main system clock: at 4.19 mhz operation) 122 m s (subsystem clock: at 32.768 khz operation) fig. 5-1 clock generator block diagram xt1 xt2 x1 x2 f xt f x scc pcc halt * stop * halt f/f stop f/f 4 q s r s r 1/4 1/8~1/4096 scc3 scc0 pcc0 pcc1 pcc2 pcc3 q selector f xx 1/2 1/6 frequency divider selector watch timer timer/pulse generator subsystem clock oscillator main system clock oscillator oscillation stop frequency divider ?fip controller ?basic interval timer (bt) ?timer/event counter ?serial interface ?watch timer ?int0 noise eliminator ?cpu ?int0 noise eliminator ?int1 noise eliminator f wait release signal from bt res signal (internal reset) standby release signal from interrupt control circuit pcc2 and pcc3 clear internal bus * instruction execution remarks 1. f x = main system clock frequency 2. f xt = subsystem clock frequency 3. f xx = system clock frequency 4. f = cpu clock 5. pcc: processor clock control register 6. scc: system clock control register 7. 1 clock cycle (t cy ) of f is 1 machine cycle of an instruction. for t cy , see ac characteristics in 12. electrical specifications. www.datasheet.co.kr datasheet pdf - http://www..net/ 19 m pd75216a * instruction execution 5.3 basic interval timer the basic interval timer has the following functions: interval timer operation to generate reference time watchdog timer application to detect inadvertent program loop wait time select and count upon standby mode release count contents read fig. 5-2 basic interval timer configuration internal bus f xx /2 5 f xx /2 7 f xx /2 12 from clock generator 4 btm3 btm2 btm1 btm0 btm mpx bt irqbt set bt interrupt request flag clear clear basic interval timer (8-bit frequency divider) wait release signal during standby release 8 3 vectored interrupt request signal f xx /2 9 set1 * www.datasheet.co.kr datasheet pdf - http://www..net/ 20 m pd75216a 5.4 watch timer the m pd75216a incorporates one channel of watch timer. the watch timer has the following functions. sets the test flag (irqw) at 0.5 sec intervals. the standby mode can be released by irqw. 0.5 second interval can be set with the main system clock and subsystem clock. the fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection. the fixed frequencies (2.048 khz) can be output to the p23/buz pin for use to generate buzzer sound and trim the system clock oscillator frequency. since the frequency divider can be cleared, the watch can be started from zero second. fig. 5-3 watch timer block diagram 8 internal bus wm7 wm6 wm5 wm4 wm2 wm1 wm0 p23 output latch port 2 input/output mode port2.3 bit 2 of pmgb p23/buz output buffer selector frequency divider clear (2.048 khz) 2 14 f w 2 7 f w (256 hz : 3.91 ms) f w (32.768 khz) selector wm from clock generator 16 f w 128 f xx (32.768 khz) f xt (32.768 khz) intw irqw set signal 2hz 0.5 sec wm3 remarks values at f xx = 4.194304 mhz and f xt = 32.768 khz are indicated in parentheses. www.datasheet.co.kr datasheet pdf - http://www..net/ 21 m pd75216a 5.5 timer/event counter the m pd75216a incorporates one channel of timer/event counter. the timer/event counter has the following functions. program interval timer operation event counter operation count state read function fig. 5-4 timer/event counter block diagram p13/ti0 input buffer from clock generator mpx tmn6 tmn5 tmn4 tmn3 tmn2 set1 tm0 timer operation start cp count register (8) clear 8 comparator (8) 8 8 modulo register (8) 8 8 internal bus tmod0 match irqt0 clear t0 tmn7 tmn1 tmn0 * intt0 irqt0 set signal ? ? ? * instruction execution. www.datasheet.co.kr datasheet pdf - http://www..net/ 22 m pd75216a 5.6 timer/pulse generator the m pd75216a incorporates one channel of timer/pulse generator which can be used as a timer or a pulse generator. the timer/pulse generator has the following functions. (a) functions available in the timer mode 8-bit interval timer operation (irqtpg generation) enabling the clock source to be varied at 5 levels square wave output to ppo pin (b) functions available in the pwm pulse generation mode 14-bit accuracy pwm pulse output to the ppo pin (used as a digital-to-analog converter and applicable to tuning) fixed time interval ( = 7.81 ms : at 4.19 mhz operation) interrupt generation if pulse output is not necessary, the ppo pin can be used as a 1-bit output port. note if the stop mode is set while the timer/pulse generator is in operation, miss-operation may result. to prevent that from occurring, preset the timer/pulse generator to the stop state using its mode register. fig. 5-5 block diagram of timer/pulse generator (timer mode) f xx 2 15 8 8 modl modh tpgm3 8 8 1/2 f x tpgm1 cp tpgm4 tpgm5 tpgm7 ppo inttpg internal bus modulo register l (8) modulo register h (8) modulo latch h (8) comparator (8) clear prescalar select latch (5) clear frequency divider (set to "1") set t f/f selector output buffer irqtpg set signal match count register (8) www.datasheet.co.kr datasheet pdf - http://www..net/ 23 m pd75216a fig. 5-6 timer/pulse generator block diagram (pwm pulse generation mode) f x tpgm1 tpgm3 8 8 modh modl modh (8) ppo tpgm5 tpgm7 inttpg 1/2 modl 7-2 (6) internal bus modulo register h (8) modulo register l (6) frequency divider modulo latch (14) pwm pulse generator selector output buffer (irqtpg set signal) (2) ( = 7.81 ms : at 4.19 mhz operation) 2 15 f x 5.7 serial interface the m pd75216a serial interface has the following functions. clock synchronous 8-bit send/receive operation (simultaneous send/receive) clock synchronous 8-bit serial bus operation (data input/output from the so pin. n-ch open-drain so output) start lsb/msb switching the above functions facilitates data communication with another microcomputer of m pd7500 series and 78k series via serial bus and coupling with peripheral devices. www.datasheet.co.kr datasheet pdf - http://www..net/ 24 m pd75216a fig 5-7 serial interface block diagram *1. cmos output and n-ch open drain output switchable output buffer. 2. instruction execution shift register (8) serial clock counter (3) clear overflow serial start siom7 siom6 siom5 siom4 siom3 siom2 siom1 siom0 siom set1 *2 8 8 8 p03/si p02/so p01/sck sio7 sio sio0 irqsio clear signal f xx /2 10 f xx /2 4 f mpx r s q internal bus intsio irqsio set signal so output latch *1 selector www.datasheet.co.kr datasheet pdf - http://www..net/ 25 m pd75216a 5.8 fip controller/driver the on-chip fip controller/driver has the following functions: generates the segment and digit signals by automatically reading the display data memory executing dma operation. can select up to a total of 26 display devices in the range of 9 to 16 segments and 9 to 16 digits. can apply the remaining display output as static output. can adjust the brightness at 8 levels using the dimmer function. can apply key scan operations. ? generates interrupt at the key scan timing (irqks) ? can generate key scan data output from the segment output pin. owns the high-voltage output pin (40 v) which can directly drive the fip. ? segment special pins (s0 to s9) : v od = 40 v, i od = 3 ma ? digit output pins (t0 to t15) : v od = 40 v, i od = 15 ma can incorporate pull-down resistors bit-wise as mask options. differences between m pd75261a and m pd75238 display output function are shown in table 5-2. table 5-2 differences between m pd75216a and m pd75238 display output function fip output total : 34 segment output : 9 to 24 digit output : 9 to 16 1a0h to 1ffh s0 to s23 (port10 to port15) ks0 to ks2 m pd75216a fip output total : 26 segment output : 9 to 16 digit output : 9 to 16 1c0h to 1ffh s12 to s15 (porth) ks0, ks1 high-voltage output display display data area output dual-function pin key scan register m pd75238 www.datasheet.co.kr datasheet pdf - http://www..net/ 26 m pd75216a 4 4 4 10 12 4 4 4 4 4 4 2 10 2 2 4 2 10 10 intks v load t0-t9 t13/s12/ph0- t10/s15/ph3 t15/s10, t14/s11 s0-s9 internal bus selector selector segment data latch (16) display data memory (64 4 bits) key scan registers (ks0, ks1) port h digit signal generator irqks generation signal key scan flag (ksf) display mode register digit select register dimmer select register high-voltage output buffer v pre fig. 5-8 fip controller/driver block diagram note the fip controller/driver can only operate in the high and intermediate-speeds (pcc = 0011b or 0010b) of the main system clock (scc.0 = 0). it may cause errors with any other clock or in the standby mode. thus, be sure to stop fip controller operation (dspm.3 = 0) and then shift the unit to any other clock mode or the standby mode. www.datasheet.co.kr datasheet pdf - http://www..net/ 27 m pd75216a 5.9 power-on flag (mask option) the power-on flag (ponf) is automatically set (1) when the power-on reset circuit is activated and the power- on reset signal is generated (see fig. 8-1 reset signal generator ). the ponf is mapped at bit 0 of address fd1h in the data memory space and can be tested by the memory bit manipulation instructions (skt, skf, sktclr) or cleared (clr1). note the ponf cannot be set by set1 instruction. www.datasheet.co.kr datasheet pdf - http://www..net/ 28 m pd75216a 6. interrupt functions the m pd75216a has eight types of interrupt sources and can generate multiple interrupts with priority order. it is also equipped with two types of test sources. int2 is an edge detected testable input. the m pd75216a interrupt control circuit has the following functions: hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt enable flag (ie ) and the interrupt master enable flag (ime). function of setting any interrupt start address. multiple interrupt function which can specify priority order with the interrupt priority select register (ips). interrupt request flag (irq ) test function. (interrupt generation can be checked by software.) standby mode release function. (interrupt to be released by interrupt enable flag can be selected.) www.datasheet.co.kr datasheet pdf - http://www..net/ 29 m pd75216a fig. 6-1 interrupt control circuit block diagram * noise eliminator 4 2 (ime) ips ist decoder 2 2 im1 im0 irqbt int4 /p00 int0 /p10 int1 /p11 irq4 irq0 irq1 irqsio irqt0 irqtpg int bt intsio intt0 inttpg vrqn internal bus vector table address generator circuit priority control circuit standby release signal interrupt enable flag (ie xxx ) edge detection circuit edge detection circuit both edges detection circuit int2 /p12 rising edge detection circuit intks irqw * * irqks irq2 intw www.datasheet.co.kr datasheet pdf - http://www..net/ 30 m pd75216a 7. standby functions two standby modes (stop mode and halt mode) are available for the m pd75216a to decrease power consumption in the program standby mode. table 7-1 operation status in standby mode halt mode halt instruction setting enabled with either main system clock or subsystem clock. stops only with cpu clock f (oscillation continued). operation (irqbt set at reference time intervals). operation enabled when serial clock other than f is specified. operation enabled. operation enabled. operation enabled. set instruction system clock when set clock oscillator basic interval timer serial interface timer/event counter timer/pulse generator watch timer fip controller/driver cpu stop mode stop instruction setting enabled only with main system clock. oscillation stops only with main system clock. operation stopped. operation enabled only when external sck input is selected for serial clock. operation enabled only when ti0 pin input is specified for count clock. operation stopped. operation enabled only f xt is selected for count clock. operating state operation disabled (display off mode set before disabling). operation stopped. release signal interrupt request signal (except int0, int1, int2) enabled by interrupt enable flag or reset input. www.datasheet.co.kr datasheet pdf - http://www..net/ 31 m pd75216a 8. reset functions the reset signal (res) generator has a configuration shown in fig. 8-1. fig. 8-1 reset signal generator the power-on reset generator is a circuit to generate a one-shot pulse upon detection of the start-up of the power voltage. this pulse is used in the following three ways according to swa, swb mask option specification shown in fig. 8-1. (refer to 10. mask option selection. reset power-on reset generator mask option internal reset signal (res) power-on flag (ponf) internal bus bit manipulation instruction execution swa swb www.datasheet.co.kr datasheet pdf - http://www..net/ 32 m pd75216a fig. 8-2 reset operation by power-on reset (31.3ms:4.19mhz) wait 0 v halt mode operating mode internal reset operation * internal reset signal (res) supply voltage * wait time does not include a time from res signal generation to oscillation start. fig. 8-3 reset operation by reset input (31.3ms:4.19mhz) wait reset input operating mode or standby mode halt mode operating mode internal reset operation each hardware state after reset operation is shown in table 8-1. www.datasheet.co.kr datasheet pdf - http://www..net/ 33 m pd75216a table 8-1 hardware statuses after reset counter (bt) mode register (btm) counter (t0) modulo register (tmod0) mode register (tm0) modulo register (modh, modl) mode register (tpgm) mode register (wm) shift register (sio) mode register (siom) processor clock control register (pcc) system clock control register (scc) interrupt request flag (irq ) interrupt enable flag (ie ) priority select register (ips) int0 and int1 mode registers (im0, im1) output buffer output latch input/output mode register (pmga, pmgb) output latch display mode register (dspm) digit select register (digs) dimmer select register (dims) display data memory output buffer sets the low-order 6 bits of program memory address 0000h to pc 13-8 and the contents of address 0001h to pc 7-0 . hold 0 0 sets bit 6 of program memory address 0000h to rbe and bit 7 to mbe. undefined hold *1 hold 0, 0 undefined 0 0 ffh 0 hold 0 0 hold only bit 4 set to 1, other bits set to 0 0 0 reset (0) 0 0 0, 0 off clear (0) 0 hold 0 1000b 0 hold off hold program counter (pc) carry flag (cy) skip flag (sk0 to sk2) interrupt status flag (ist0, ist1) bank enable flags (mbe, rbe) stack pointer (sp) data memory (ram) general registers (x, a, h, l, d, e, b, c) bank select registers (mbs, rbs) psw basic interval timer timer/event counter timer/pulse generator watch timer serial interface clock generator interrupt digital port port h fip controller/ driver power on flag (ponf) same as left undefined 0 0 same as left undefined undefined undefined 0, 0 undefined 0 0 ffh 0 undefined 0 0 undefined only bit 4 set to 1, other bits set to 0 0 0 reset (0) 0 0 0, 0 off clear (0) 0 undefined 0 1000b 0 undefined off 1 or undefined *2 hardware reset input in standby mode reset input upon power-on reset or in operation *1. data of data memory addresses 0f8h to 0fdh becomes indeterminate by reset input. 2. 1 upon power-on reset, indeterminate after reset input in operation. www.datasheet.co.kr datasheet pdf - http://www..net/ 34 m pd75216a 9. instruction set (1) operand identifier and description enter an operand in the operand column of each instruction using the description method relating to the operand identifier of the instruction (for details, refer to ra75x assembler package users manual language volume (eeu-730) ). if more than one description method is available, select one. capital alphabetic letters, plus and minus signs are keywords. describe them as they are. in the case of immediate data, describe appropriate numerical values or labels. symbols can be described as labels in place of mem, fmem, pmem, bit, etc. (for details, refer to m pd75216a users manual (iem-988) ). available labels are limited for fmem and pmem. identifier description method reg x, a, b, c, d, e, h, l reg 1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp xa, bc, de, hl, xa, bc, de, hl rp1 bc, de, hl, xa, bc, de, hl rpa hl, hl+, hl-, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label * bit 2-bit immediate data or label fmem fb0h to fbfh and ff0h to fffh immediate data or labels pmem fc0h to fffh immediate data or labels addr 0000h to 3f7fh immediate data or labels caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (bit0 = 0) or label portn port0 to port6 ie iebt, iesio, iet0, ietpg, ie0, ie1, ieks, iew, ie4 rbn rb0 to rb3 mbn mb0, mb1, mb15 * for 8-bit data processing, only even addresses can be specified. www.datasheet.co.kr datasheet pdf - http://www..net/ 35 m pd75216a (2) legend for operation description a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa : expanded register pair (xa) bc : expanded register pair (bc) de : expanded register pair (de) hl : expanded register pair (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 6) ime : interrupt master enable flag ips : interrupt priority select register ie : interrupt enable flag rbs : register bank select register mbs : memory bank select register pcc : processor clock control register ? : address and bit delimiter ( ) : contents addressed by h : hexadecimal data www.datasheet.co.kr datasheet pdf - http://www..net/ 36 m pd75216a (3) description of symbols in the addressing area column data memory addressing program memory addressing * 1 mb = mbe ? mbs (mbs = 0, 1, 15) * 2 mb = 0 * 3 mbe = 0 : mb = 0 (00h to 7fh) mb = 15 (80h to ffh) mbe = 1 : mb = mbs (mbs = 0, 1, 15) * 4 mb = 15, fmem = fb0h to fbfh, ff0h to fffh * 5 mb = 15, pmem = fc0h to fffh * 6 addr = 0000h to 3f7fh * 7 addr = (current pc) C 15 to (current pc) C 1, (current pc) + 2 to (current pc) + 16 * 8 caddr = 0000h to 0fffh (pc 13, 12 = 00b) or 1000h to 1fffh (pc 13, 12 = 01b) or 2000h to 2fffh (pc 13, 12 = 10b) or 3000h to 3f7fh (pc 13, 12 = 11b) * 9 faddr = 0000h to 07ffh *10 taddr = 0020h to 007fh remarks 1. mb indicates accessible memory bank. 2. in *2, mb = 0 irrespective of mbe and mbs. 3. in *4 and *5, mb = 15 irrespective of mbe and mbs. 4. *6 to *10 indicate addressable areas. (4) description of the machine cycle column s indicates the number of machine cycles required for skip operation by an instruction having skip function. the s value varies as follows: ? when not skipped ................................................................................................... s = 0 ? when 1-byte or 2-byte instructions are skipped ................................................. s = 1 ? when 3-byte instructions are skipped (br !addr, call !addr instruction) ..... s = 2 note geti instruction is skipped in one machine cycle. one machine cycle is equal to one cycle(=t cy ) of cpu clock f and three time periods are available according to pcc setting. www.datasheet.co.kr datasheet pdf - http://www..net/ 37 m pd75216a a, #n4 1 1 a ? n4 stack a reg1, #n4 2 2 reg1 ? n4 xa, #n8 2 2 xa ? n8 stack a hl, #n8 2 2 hl ? n8 stack b rp2, #n8 2 2 rp2 ? n8 a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2 + s a ? (hl), then l ? l+1 *1 l = 0 a, @hlC 1 2 + s a ? (hl), then l ? lC1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 @hl, a 1 1 (hl) ? a*1 @hl, xa 2 2 (hl) ? xa *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 mem, a 2 2 (mem) ? a*3 mem, xa 2 2 (mem) ? xa *3 a, reg 2 2 a ? reg xa, rp' 2 2 xa ? rp' reg1, a 2 2 reg1 ? a rp'1, xa 2 2 rp'1 ? xa a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2 + s a ? (hl), then l ? l+1 *1 l = 0 a, @hlC 1 2 + s a ? (hl), then l ? lC1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 a, reg1 1 1 a ? reg1 xa, rp' 2 2 xa ? rp' xa, @pcde 1 3 xa ? (pc 13C8 +de) rom xa, @pcxa 1 3 xa ? (pc 13C8 +xa) rom machine cycle skip condition addressing area no. of bytes transfer note 1. instruction group 2. table reference mnemonic operands operation note 1 mov xch movt note 2 www.datasheet.co.kr datasheet pdf - http://www..net/ 38 m pd75216a machine cycle skip condition addressing area no. of bytes cy, fmem.bit 2 2 cy ? (fmem.bit) *4 cy, pmem.@l 2 2 cy ? (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? (h+mem 3C0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) ? cy *4 pmem.@l, cy 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? cy *5 @h+mem.bit, cy 2 2 (h+mem 3C0 .bit) ? cy *1 a, #n4 1 1 + s a ? a+n4 carry xa, #n8 2 2 + s xa ? xa+n8 carry a, @hl 1 1 + s a ? a+(hl) *1 carry xa, rp' 2 2 + s xa ? xa+rp' carry rp'1, xa 2 2 + s rp'1 ? rp'1+xa carry a, @hl 1 1 a, cy ? a+(hl)+cy *1 xa, rp' 2 2 xa, cy ? xa+rp'+cy rp'1, xa 2 2 rp'1, cy ? rp'1+xa+cy a, @hl 1 1 + s a ? aC(hl) *1 borrow xa, rp' 2 2 + s xa ? xaCrp' borrow rp'1, xa 2 2 + s rp'1 ? rp'1Cxa borrow a, @hl 1 1 a, cy ? aC(hl)Ccy *1 xa, rp' 2 2 xa, cy ? xaCrp'Ccy rp'1, xa 2 2 rp'1, cy ? rp'1CxaCcy a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa bit transfer operation note instruction group mnemonic operand operation note mov1 adds addc subs subc and or xor www.datasheet.co.kr datasheet pdf - http://www..net/ 39 m pd75216a a11cy ? a 0 , a 3 ? cy, a nC1 ? a n a22a ? a reg 1 1 + s reg ? reg+1 reg = 0 rp1 1 1 + s rp1 ? rp1+1 rp1 = 00h @hl 2 2 + s (hl) ? (hl)+1 *1 (hl) = 0 mem 2 2 + s (mem) ? (mem)+1 *3 (mem) = 0 reg 1 1 + s reg ? regC1 reg = fh rp' 2 2 + s rp' ? rp'C1 rp = ffh reg, #n4 2 2 + s skip if reg = n4 reg = n4 @hl, #n4 2 2 + s skip if (hl) = n4 *1 (hl) = n4 a, @hl 1 1 + s skip if a = (hl) *1 a = (hl) xa, @hl 2 2 + s skip if xa = (hl) *1 xa = (hl) a, reg 2 2 + s skip if a = reg a = reg xa.rp' 2 2 + s skip if xa = rp' xa = rp' cy 1 1 cy ? 1 cy 1 1 cy ? 0 cy 1 1 + s skip if cy = 1 cy = 1 cy 1 1 cy ? cy machine cycle skip condition addressing area no. of bytes rorc not note 2 increment/decrement compare set1 clr1 skt not1 carry flag manipulation note 1. instruction group 2. accumulator manipulation operands mnemonic operation note 1 incs decs ske www.datasheet.co.kr datasheet pdf - http://www..net/ 40 m pd75216a mem.bit 2 2 (mem.bit) ? 1*3 fmem.bit 2 2 (fmem.bit) ? 1*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? 1*5 @h + mem.bit 2 2 (h+mem 3C0 .bit) ? 1*1 mem.bit 2 2 (mem.bit) ? 0*3 fmem.bit 2 2 (fmem.bit) ? 0*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? 0*5 @h+mem.bit 2 2 (h+mem 3C0 .bit) ? 0*1 mem.bit 2 2 + s skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2 + s skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@l 2 2 + s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 )) = 1 *5 (pmem.@l) = 1 @h+mem.bit 2 2 + s skip if (h+mem 3C0 .bit) = 1 *1 (@h+mem.bit) = 1 mem.bit 2 2 + s skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2 + s skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@l 2 2 + s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 )) = 0 *5 (pmem.@l) = 0 @h+mem.bit 2 2 + s skip if (h+mem 3C0 .bit) = 0 *1 (@h+mem.bit) = 0 fmem.bit 2 2 + s skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@l 2 2 + s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=1 and clear *5 (pmem.@l) = 1 @h+mem.bit 2 2 + s skip if (h+mem 3C0 .bit)=1 and clear *1 (@h+mem.bit)=1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 addr pc 13C0 ? addr *6 (optimum instruction is selected from among br !addr, brcb !caddr and br $addr by an assembler.) !addr 3 3 pc 13C0 ? addr *6 $addr 1 2 pc 13C0 ? addr *7 !caddr 2 2 pc 13C0 ? pc 13,12 +caddr 11C0 *8 pcde 2 3 pc 13C0 ? pc 13C8 +de pcxa 2 3 pc 13C0 ? pc 13C8 +xa machine cycle skip condition addressing area no. of bytes memory bit manipulation brcb branch note instruction group mnemonic operands operation note set1 clr1 skt skf sktclr and1 or1 xor1 br br www.datasheet.co.kr datasheet pdf - http://www..net/ 41 m pd75216a !addr 3 3 (spC4) (spC1) (spC2) ? pc 11C0 *6 (spC3) ? mbe, rbe, pc 13, 12 pc 13C0 ? addr, sp ? spC4 !faddr 2 2 (spC4) (spC1) (spC2) ? pc 11C0 *9 (spC3) ? mbe, rbe, pc 13, 12 pc 13C0 ? 000, faddr, sp ? spC4 1 3 mbe, rbe, pc 13, 12 ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2) sp ? sp+4 mbe, rbe, pc 13, 12 ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2) sp ? sp+4 then skip unconditionally 13 , , pc 13, 12 ? (sp+1) pc 11C0 ? (sp) (sp+3) (sp+2) psw ? (sp+4) (sp+5), sp ? sp+6 rp 1 1 (spC1) (spC2) ? rp, sp ? spC2 bs 2 2 (spC1) ? mbs, (spC2) ? rbs, sp ? spC2 rp 1 1 rp ? (sp+1) (sp), sp ? sp+2 bs 2 2 mbs ? (sp+1), rbs ? (sp), sp ? sp+2 2 2 ime (ips.3) ? 1 ie 22ie ? 1 2 2 ime (ips.3) ? 0 ie 22ie ? 0 a, portn 2 2 a ? portn (n = 0 to 6) xa, portn 2 2 xa ? portn+1, portn (n = 4) portn, a 2 2 portn ? a (n = 2 to 6) portn, xa 2 2 portn+1, portn ? xa (n = 4) 2 2 set halt mode (pcc.2 ? 1) 2 2 set stop mode (pcc.3 ? 1) 1 1 no operation rbn 2 2 rbs ? n (n = 0 to 3) mbn 2 2 mbs ? n (n = 0, 1, 15) * 10 machine cycle skip condition addressing area no. of bytes subroutine stack control * interrupt control input/output cpu control * halt stop nop * mbe = 0 or mbe = 1 and mbs = 15 must be set for execution of in/out instruction. note instruction group special mnemonic operands operation note 13 + s call callf ret rets reti push pop ei di in out sel unconditional www.datasheet.co.kr datasheet pdf - http://www..net/ 42 m pd75216a 3 ? tbr instruction pc 13C0 ? (taddr) 4C0 +(taddr+1) ? tcall instruction (spC4)(spC1)(spC2) ? pc 11C0 (spC3) ? mbe, rbe, pc 13, 12 pc 13C0 ? (taddr) 4C0 +(taddr+1) sp ? spC4 ? (taddr) (taddr+1) instruction depends on executed in the case of instructions instruction except tbr and referred to. tcall instructions machine cycle skip condition addressing area no. of bytes special ---------------------------------------------------- ------------------------ ------------------------ ---------------------------------------------------- * tbr and tcall instructions are assembled pseudo-instructions to define the geti instruction table. note instruction group mnemonic operands operation note 1 geti * taddr *10 www.datasheet.co.kr datasheet pdf - http://www..net/ 43 m pd75216a 10. mask option selection the m pd75216a has the following mask options enabling or disabling on-chip components. (1) pin note 1. in a system not using subsystem clocks, power consumption in the stop mode can be decreased by removing the feedback resistor from the oscillator. 2. the feedback resistor must be incorporated when using subsystem clock. (2) power-on reset generator, power-on flag (ponf) one of the following three can be selected. pin mask option p60 to p63 t0/t9 t10/s15/ph3 to t13/s12/ph0 t14/s11, t15/s10 s0 to s9 xt1, xt2 pull-up resistor incorporation enabled bit-wise deletion of subsystem clock oscillator feedback resistor possible switch selection (see fig. 8-1 ) swa swb on on off on off off incorporated incorporated not incorporated incorporated incorporated not incorporated generate automatically not generate automatically CCCCC power-on reset generator power-on flag (ponf) internal reset signal (res) www.datasheet.co.kr datasheet pdf - http://www..net/ 44 m pd75216a main power supply power failure detection lpf electronic tuner tape count pulse tape up/down sck system controller so microcomputer si pd75104/75106 eeprom m pd6252 m x1 x2 xt1 xt2 bz piezoelectric buzzer super capacitor fluorescent display panel (fip) 16 segments 10 digits 10 16 key matrix (16 4) remote controlled signal pc2800a m timer tuner remote controlled reception tape counter int4 ppo int1 sck so v dd v ss t0?9 s0?15 port6 int0 buz ? ? ? ? ? ? ? ? ? ? ? ? + 11. application block diagram 11.1 vcr timer tuner m pd75216a www.datasheet.co.kr datasheet pdf - http://www..net/ 45 m pd75216a x1 x2 bz fluorescent display panel (fip) 12 segments 14 digits 14 12 key matrix (12 4) remote controlled signal pc2800a m sck si/so buz t0?13 s0?11 port6 int0 sio servo control ic loading circuit 11.2 cd player m pd75216a x1 x2 xt1 xt2 bz fluorescent display panel (fip) 10 segments 16 digits 16 10 key matrix (10 4) main power supply power failure detection ram int4 v dd v ss t0?15 s0?9 ppo + printer m pd75216a 11.3 ecr www.datasheet.co.kr datasheet pdf - http://www..net/ 46 m pd75216a v dd v load v pre v i v o v od i oh i ol p t t opt t stg unit rating test conditions 12. electrical specifications absolute maximum ratings (ta = 25 c) power supply voltage input voltage output voltage output current high output current low total loss *1 operating temperature storage temperature pins except display output pins display output pins 1 pin except display output pins s0 to s9 1 pin t0 to t15 1 pin total of pins except display output pins total of display output pins 1 pin total of pins plastic qfp plastic shrink dip C0.3 to +7.0 v dd C40 to v dd +0.3 v dd C12 to v dd +0.3 C0.3 to v dd +0.3 C0.3 to v dd +0.3 v dd C40 to v dd +0.3 C15 C15 C30 C20 C120 17 60 450 600 C40 to +85 C65 to +150 v v v v v v ma ma ma ma ma ma ma mw mw c c symbol parameter note product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. in other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore, the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. operating voltage (ta = C40 to +85 c) parameter cpu *2 display controller time/pulse generator other hardware *2 test conditions min. *3 4.5 4.5 2.7 max. unit 6.0 6.0 6.0 6.0 v v v v input capacitance except display output display output input /output capacitance unit output capacitance parameter symbol c in c io pf pf pf pf max. 15 15 35 15 typ. min. test conditions f = 1 mhz unmeasured pin returned to 0 v c out capacitance ( ta = 25 c, v dd = 0 v ) h www.datasheet.co.kr datasheet pdf - http://www..net/ 47 m pd75216a *1. calculation of total loss design so that the sum of the following three power consumption values for the m pD75216ACW/gf will be less than the total loss p t (it is recommended to use the system with 80 % or less of the rating). cpu loss : given as v dd (max.) i dd1 (max.) output pin loss : there are normal output pin loss and display output pin loss. it is necessary to add a loss derived from the flow of maximum current to each output pin. a pull-down register loss : power loss due to a pull-down resistor incorporated in the display output pin by mask option. example suppose 4-led output with 9 seg 11 digit , v dd = 5 v + 10 % and 4.19 mhz oscillation and let a current of 3 ma, 15 ma and up to 10 ma flow to the segment pin, timing pin and led output pin, respectively. further, let the voltage of fluorescent display tube (v load voltage) be C30 v and normal voltage be small. cpu loss : 5.5 v 9.0 ma = 49.5 mw pin loss : segment pin ..... 2v 3 ma 9 = 54 mw timing pin ......... 2v 15 ma = 30 mw led output ........ a pull-down resistor loss ........ pt = + + a = 690.6 mw in this example, since the allowable total loss is 600 mw for the shrink dip package, it is necessary to decrease power consumption by decreasing the number of on-chip pull-down resistors. in this example, power consumption can be adjusted to 577.8 mw by incorporating pull-down resistors in only 11 digit outputs and 7 segment outputs and externally mounting pull-down resistors to the 2 remaining segment outputs. 2. except the system clock oscillator, display controller and timer/pulse generator. 3. the operating voltage range varies depending on the cycle time. refer to the section describing ac characteristics. 2 v 10 ma 4 = 53 mw 10 15 (30 + 5.5v) 2 25 k w 10 = 504.1 mw h www.datasheet.co.kr datasheet pdf - http://www..net/ 48 m pd75216a x1 x2 c1 c2 x1 x2 c1 c2 main system clock oscillator characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v ) v dd = oscillation voltage range after v dd reaches the minimum value in the oscillation voltage range v dd = 4.5 to 6.0 v oscillator frequency (f xx ) *2 oscillation stabilization time *3 oscillator frequency (f xx ) *2 oscillation stabilization time *3 x1 input frequency (f x ) *2 x1 input high and low level widths (t xh , t xl ) x1 x2 m pd74hcu04 2.0 2.0 2.0 100 4.19 5.0 4 5.0 *4 10 30 5.0 250 mhz ms mhz ms ms mhz ns min. typ. max. unit test conditions parameter recommended circuit resonator ceramic resonator *1 crystal resonator *1 external clock *1. refer to recommended oscillator constants . 2. oscillator characteristics only. refer to the description of ac characteristics for details of instruction execution time. 3. time required for oscillation to become stabilized after v dd reaches the minimum value in the oscillation voltage range or stop mode release. 4. when oscillator frequency is 4.19 < f xx < C 5.0 mhz, do not select pcc = 0011 as instruction execution time. if pcc = 0011 is selected, 1 machine cycle becomes less than 0.95 m s, with the result that the specified min. value of 0.95 m s cannot be observed. note when the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. ? the wiring should be kept as short as possible. ? no other signal lines should be crossed. keep away from lines carrying a high fluctuating current. ? the oscillator capacitor grounding point should always be at the same potential as v ss . do not connect to a ground pattern carrying a high current. ? a signal should not be taken from the oscillator. h www.datasheet.co.kr datasheet pdf - http://www..net/ 49 m pd75216a xt1 xt2 c3 c4 r subsystem clock oscillator characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) oscillator frequency (f xt ) *2 oscillation stabilization time *3 xt1 input frequency (f xt ) xt1 input high and low level widths (t xth , t xtl ) v dd = 4.5 to 6.0 v 32.768 1.0 35 2 10 100 32 khz s s khz m s crystal resonator *1 external clock 32 32 10 min. typ. max. unit test conditions parameter recommended circuit resonator *1. recommended resonators are shown in following page. 2. oscillator characteristics only. refer to the description of ac characteristics for instruction execution time. 3. oscillation stabilization time is a time required for oscillation to become stabilized after v dd reaches the minimum value in the oscillation voltage range. note when the subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. ? the wiring should be kept as short as possible. ? no other signal lines should be crossed. keep away from lines carrying a high fluctuating current. ? the oscillator capacitor grounding point should always be at the same potential as v ss . do not connect to a ground pattern carrying a high current. ? a signal should not be taken from the oscillator. the subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. xt1 leave open xt2 h www.datasheet.co.kr datasheet pdf - http://www..net/ 50 m pd75216a csa 2.00mg csa 4.19mg csa 4.91mg cst 2.00mg cst 4.19mg cst 4.91mg kbrC2.0ms kbrC4.0ms kbrC4.19ms kbrC4.19ms fcr 3.58m2 fcr 4.00m2 fcr 4.19m2 fcr 4.19mc c1 c2 min. max. 30 30 external capacitance (pf) oscillation voltage range (v) manufacturer product name remarks recommended oscillator constants main system clock : ceramic oscillator (ta = C40 to +85 c) not required 47 33 30 not required not required 47 33 30 not required 4.0 4.0 6.0 6.0 6.0 4.0 on-chip c type on-chip c type murata mfg. co., ltd. kyocera corp. tdk main system clock : crystal resonator (ta = C40 to +85 c) c1 c2 min. max. external capacitance (pf) oscillation voltage range (v) load capacitance cl (pf) 2.00 4.19 4.91 kinseki hcC18/u hcC49/u hc-43/u 16 20 20 4.0 6.0 manufacturer remarks frequency (mhz) holder external capacitance (pf) c4 (pf) r (k w ) min. (v) max. (v) oscillation voltage range (v) subsystem clock : 32.768 khz crystal resonator (ta = C10 to +60 c) c3 (pf) pC3 cfsC308 kinseki citizen watch co. 12 14 22 22 22 33 330 330 2.7 6.0 manufacturer remarks load capacitance cl (pf) model name note carry out fine adjustment of crystal oscillator frequency on the external capacitance c1. note carry out fine adjustment of crystal oscillator frequency on the external capacitance c3. www.datasheet.co.kr datasheet pdf - http://www..net/ 51 m pd75216a 0.7 v dd 0.75 v dd v dd C0.4 0.65 v dd 0.7 v dd 0 0 0 v dd C1.0 v dd C0.5 C3 C1.5 C15 C7 20 20 25 v v v v v v v v v v v v v m a m a m a m a m a m a m a ma ma ma ma k w k w k w ma ma m a m a m a m a m a m a 0.4 C5.5 C3.5 C22 C15 80 70 3.0 0.55 600 200 40 5 0.5 0.1 v ih1 v ih2 v ih3 v il1 v il2 v il3 v ol i lih1 i lih2 i lil1 i lil2 i loh i lol1 i lol2 all output pins display output except display output x1, x2, xt1 x1, x2, xt1 v dd = 4.5 to 6.0v, i oh = C1 ma v dd = 4.5 to 6.0v, i ol = 15 ma v dd = 4.5 to 6.0v, i ol = 1.6 ma all output pins except below ports 0, 1, 6, reset x1, x2, xt1 except below ports 0, 1, reset x1, x2, xt1 dc characteristics (ta = C40 to 85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions port 6 v ih4 input voltage high input voltage low v dd = 4.5 to 6.0 v i oh = C100 m a output voltage high v oh ports 4, 5 i ol = 400 m a all output pins except x1,x2,xt1 except x1,x2,xt1 output voltage low input leakage current high s0 to s9 t0 to t15 v in = v dd v in = 0 v v out = v dd v out = 0 v v out = v load = v dd C 35 v v dd = 4.5 to 6.0 v v od = v dd C 2 v v pre = v dd C 9 1 v *1 v pre = 0 v v pre = 0 v v pre = v dd C 9 1 v *1 port 6 v in = v dd v dd = 4.5 to 6.0 v display output v od C v load = 35 v v dd = 5 v 10 % *3 v dd = 3 v 10 % *4 v dd = 5 v 10 % v dd = 3 v 10 % v dd = 3 v 10 % halt mode halt mode v dd = 3 v 10 % v dd = 5 v 10 % v dd = 3 v 10 % 4.19 mhz crystal oscillation c1 = c2 = 15pf 32 khz crystal oscillation *5 xt1 = 0 v stop mode i dd5 i dd4 i dd3 i dd2 i dd1 r l r p6 i od input leakage current low output leakage current high output leakage current low display output current built-in pull-down resistor (mask option) supply current *2 min. typ. v dd v dd v dd v dd v dd 0.3 v dd 0.2 v dd 0.4 2.0 0.4 0.5 3 20 C3 C20 3 C3 C10 200 1000 135 9.0 1.5 1800 600 120 15 20 10 max. unit www.datasheet.co.kr datasheet pdf - http://www..net/ 52 m pd75216a *1. the following external circuit is recommended. 2. current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included. 3. when the processor clock control register (pcc) is set to 0011 and is operated in the high-speed mode. 4. when the pcc register is set to 0000 and is operated in the low-speed mode. 5. when the system clock control register (scc) is set to 1001 and is operated with the subsystem clock with main system clock oscillation stopped. remarks start the power supply smoothly. m pd75216a power-on reset circuit characteristics (mask option) (ta = C40 to +85 c) power-on reset operating voltage high power-on reset operating voltage low power supply voltage off time power supply voltage rise time power-on reset circuit *2 current consumption v ddh t r v ddl t off i ddpr v dd = 5 v 10 % v dd = 2.7 v parameter symbol test conditions min. typ. max. unit 4.5 0 10 1 10 2 6.0 0.2 *1 100 20 v v m s m a m a s *1. 2 17 /f xx (31.3 ms at f xx = 4.19 mhz) 2. current with on-chip power-on reset circuit or power-on flag. v dd v ddh v ddl t r t off v dd v pre v load v ss rd9, 1el 68 k w +5 v ?0 v rd9, 1el : zener diode (nec) zener voltage = 8.29 to 9.30 v www.datasheet.co.kr datasheet pdf - http://www..net/ 53 m pd75216a input output input output ac characteristics (ta = C40 to +85 c , v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit operation with main system clock operation with sub- system clock t cy cpu clock cycle time (minimum instruction execution time = 1 machine cycle) *1 ti0 input frequency v dd = 4.5 to 6.0 v ti0 input high and low- level widths f ti v dd = 4.5 to 6.0 v input output input output v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v int0 int1 int2, 4 t tih , t til t kcy t rsl t inth , t intl t kso t ksi t sik t kh , t kl reset low-level width interrupt input high and low-level widths sck cycle time sck high and low-level widths si setup time (to sck - ) si hold time (from sck - ) so output delay time from sck 0.95 3.8 114 0 0 0.83 3 0.8 0.95 3.2 3.8 0.4 t kcy /2C50 1.6 t kcy /2C150 100 400 *2 2t cy 10 10 300 1000 122 32 32 125 0.6 165 m s m s m s mhz khz m s m s m s m s m s m s m s ns m s ns m s m s m s m s ns ns ns ns www.datasheet.co.kr datasheet pdf - http://www..net/ 54 m pd75216a *1. cpu clock ( f ) cycle time is determined by the oscillator frequency of the connected resonator, the system clock control register (scc) and the processor clock control register (pcc). the cycle time t cy characteristics for power supply voltage v dd when the main system clock is in operation is shown below. 2. 2t cy or 128/f xx is set by interrupt mode register (im0) setting. 40 32 30 6 5 4 3 2 1 0.5 0 1 2 3 4 5 6 operation guaranteed range t cy vs v dd (main system clock in operation) power supply voltage v dd [v] cycle time t cy [ m s] www.datasheet.co.kr datasheet pdf - http://www..net/ 55 m pd75216a ac timing test points (except x1 and xt1 inputs) clock timing ti0 timing 0.75 v dd 0.2 v dd 0.75 v dd 0.2 v dd test points 1/f x t xl t xh v dd - 0.4 v 0.4 v x1 input 1/f xt t xtl t xth v dd - 0.4 v 0.4 v xt1 input 1/f ti t til t tih ti0 www.datasheet.co.kr datasheet pdf - http://www..net/ 56 m pd75216a interrupt input timing reset input timing serial transfer timing t kso sck si so input data output data t kcy t kh t kl t sik t ksi int0,1,2,4 t intl t inth reset t rsl www.datasheet.co.kr datasheet pdf - http://www..net/ 57 m pd75216a 2.0 6.0 v v dddr = 2.0v 0.1 10 m a 0 m s release by reset 2 17 /f x ms release by interrupt request *3 ms data memory stop mode low power supply voltage data retention characteristics (ta = C40 to +85 c) parameter symbol test conditions min. typ. max. unit data retention power supply voltage data retention power supply current *1 t srel t wait v dddr i dddr release signal set time oscillation stabilization wait time *2 data retention timing (stop mode release by reset) stop instruction execution v dd v dddr operating mode halt mode stop mode data retention mode t wait reset t srel internal reset operation btm3 btm2 btm1 btm0 wait time (values at f xx = 4.19 mhz in parentheses) 0 002 20 /f xx (approx. 250 ms) 0 112 17 /f xx (approx. 31.3 ms) 1 012 15 /f xx (approx. 7.82 ms) 1 112 13 /f xx (approx. 1.95 ms) *1. current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included. 2. oscillation stabilization wait time is time to stop cpu operation to prevent unstable operation upon oscillation start. 3. according to the setting of the basic interval timer mode register (btm) (see below). www.datasheet.co.kr datasheet pdf - http://www..net/ 58 m pd75216a data retention timing (standby release signal: stop mode release by interrupt signal) stop instruction execution v dd v dddr standby release signal (interrupt request) operating mode halt mode stop mode data retention mode t wait t srel www.datasheet.co.kr datasheet pdf - http://www..net/ 59 m pd75216a 13. characteristic curves i dd vs v dd supply voltage v dd [v] supply current i dd [ m a] remarks values of the processor clock control register (pcc) is indicated in parenthesis. high-speed mode (0011) medium-speed mode (0010) low-speed mode (0000) halt mode (0100) subsystem clock operating mode subsystem clock halt mode stop mode (1000) power-on reset circuit and power-on flag incorporated ? ? ? ? ? ? ? ? ? ? 330 k w 32.768 khz 33 pf 22 pf 15 pf 4.19 mhz 15 pf 6 5 4 3 2 1 0 1 10 5 100 50 1000 500 5000 x1 x2 xt1 xt2 (ta = 25 c) www.datasheet.co.kr datasheet pdf - http://www..net/ 60 m pd75216a i ol vs v ol (ports 0, 2, 3, 6) output current low i ol [ma] output voltage low v ol [v] i oh vs (v dd C v oh ) (ports 0, 2, 3, 6) v dd C v oh [v] output current high i oh [ma] ?0 ?5 ?0 ? 0 0 1 2 3 4 5 v dd = 6 v v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2.7 v (ta = 25 ?) 20 15 10 5 0 0 1 2 3 4 5 v dd = 6 v v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2.7 v (ta = 25 ?) www.datasheet.co.kr datasheet pdf - http://www..net/ 61 m pd75216a i ol vs v ol (ports 4, 5) output current low i ol [ma] output voltage low v ol [v] i oh vs (v dd C v oh ) (ports 4, 5) v dd C v oh [v] output current high i oh [ma] 20 15 10 5 0 0 1 2 3 4 5 6 v v dd = 5 v 4 v v dd = 3 v v dd = 2.7 v (ta = 25 ?) ?0 ?5 ?0 ? 0 0 1 2 3 4 5 v dd = 6 v v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2.7 v (ta = 25 ?) www.datasheet.co.kr datasheet pdf - http://www..net/ 62 m pd75216a ?0.0 ?0.0 ?0.0 ?0.0 0 0 1 2 3 4 5 (ta = 25 ?) v dd ?v pre = 6 v v dd ?v pre = 8 v v dd ?v pre = 10 v v dd ?v pre = 4 v i od vs (v dd to v od ) (t0 to t15) v dd C v od [v] display output current i od [ma] i od vs (v dd C v od ) (s0 to s9) v dd C v od [v] display output current i od [ma] ?0.0 ?.0 0 0 1 2 3 4 5 (ta = 25 ?) v dd ?v pre = 6 v v dd ?v pre = 8 v v dd ?v pre = 10 v v dd ?v pre = 4 v www.datasheet.co.kr datasheet pdf - http://www..net/ 63 m pd75216a 14. package information a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15? 0.50?.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15? +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mil) www.datasheet.co.kr datasheet pdf - http://www..net/ 64 m pd75216a 64 pin plastic qfp (14 20) p64gf-100-3b8,3be,3br-2 item millimeters inches a b c 23.6?.4 20.0?.2 14.0?.2 0.929?.016 0.795 0.551 d 17.6?.4 0.693?.016 f 1.0 0.039 g 1.0 0.039 h 0.40?.10 0.016 i 0.20 0.008 j 1.0 (t.p.) 0.039 (t.p) k 1.8?.2 0.071 l 0.8?.2 0.031 m 0.15 0.006 n 0.10 0.004 p 2.7 0.106 q 0.1?.1 0.004?.004 r 55 55 s 3.0 max. 0.119 max. +0.008 ?.009 +0.009 ?.008 +0.004 ?.005 +0.008 ?.009 +0.009 ?.008 +0.004 ?.003 note each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. 51 52 32 64 1 20 19 33 i j m n h g f a s p k l m b c d detail of lead end q r +0.10 ?.05 www.datasheet.co.kr datasheet pdf - http://www..net/ 65 m pd75216a 64-pin ceramic qfp for es (reference) (unit : mm) 14.2 12.0 64 52 1 51 32 20 19 33 0.4 1.0 2.25 18.0 0.15 bottom view 20 note 1. care is needed since the metal cap is con- nected to pin 26 and set to the positive power supply level. 2. care is needed since the lead of the base is formed obliquely. 3. the lead length is not stipulated since the cutting of the lead ends is not progress- controlled. www.datasheet.co.kr datasheet pdf - http://www..net/ 66 m pd75216a 15. recommended soldering conditions this product should be soldered and mounted under the conditions recommended below. for details of recommended soldering conditions for the surface mounting type, refer to the document semiconductor device mount technology (iei-1207) . for soldering methods and conditions other than those recommended below, contact our salesman. table 15-1 surface mounting type conditions recommended condition symbol soldering method soldering conditions solder bath temperature: 260 c or less, duration: 10 sec. max. number of times: once, time limit: 7 days * (thereafter 10 hours prebaking required at 125 c) preheating temperature : 120 c max. (package surface temperature) package peak temperature: 230 c, duration: 30 sec. max. (at 210 c or above), number of times: once, time limit: 7 days * (thereafter 10 hours prebaking required at 125 c) package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), number of times: once, time limit: 7 days * (thereafter 10 hours prebaking required at 125 c) pin part temperature: 300 c or below , duration: 3 sec. max. (per device side) pin part heating vps infrared reflow wave soldering CCC vp15-107-1 ir-30-107-1 ws60-107-1 m pd75216agf- -3be : 64-pin plastic qfp (14 20 mm) table 15-2 insertion type soldering conditions m pD75216ACW- : 64-pin plastic shrink dip (750 mil) soldering method soldering conditions wave soldering (lead part only) solder bath temperature: 260 c or below , duration: 10 sec. max. pin part temperature: 260 c or below , duration: 10 sec. max. pin part heating note ensure that the application of wave soldering is limited to the lead part and no solder touches the main unit directly. * for the storage period after dry-pack decompression storage conditions are max. 25 c, 65 % rh. note use of more than one soldering method should be avoided (except in the case of pin part heating). notice a version of this product with improved recommended soldering condition is available. for details (improvements such as infrared reflow peak temperature extension (235 c), number of times: twice, relaxation of time limit, etc.), contact nec sales personnel. h www.datasheet.co.kr datasheet pdf - http://www..net/ 67 m pd75216a ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 20 mm) appendix a. list of m pd75216a series product functions vectored interrupt test input system clock oscillator power-on reset circuit low supply voltage data retention 16k mode/32k mode switch function operating temperature range operating voltage package product name item m pd75206 m pd75208 m pd75212a m pd75216a m pd75p216a m pd75p218 * 6016 8 8064 8 12160 8 16256 8 32640 8 369 4 497 4 512 4 1024 4 ? 0.95, 1.91, 15.3 m s (main system clock : 4.19 operation) ? 122 m s (subsystem clock : 32.768 khz operation) 33 8 serial input, timer input, interrupt input dual function ? led direct drive capability : 8 ? no pull-down resistor ? pwm/pulse output : 1 ? led direct drive capability : 4 ? no pull-down resistor ? 40 v max. ? s0 to s8, t0 to t9 : pull-down resister ? s9, t10 to t15 : open-drain output 9 to 12 segments 9 to 16 segments 9 to 16 digits 4 ? timer/pulse generator : 14 bit pwm output capability channels ? watch timer : buzzer output capability ? timer/event counter ? basic internal timer : watchdog timer application capability ? msb start/lsb start switchable ? serial bus configuration possible external : 3 , internal : 5 external : 1 , internal : 1 ? main system clock oscillation ceramic/crystal oscillation circuit : 4.194304 mhz standard ? subsystem clock oscillation crystal oscillation circuit : 32.768 khz standard incorporated (mask option) none yes (2 v) none incorporated rom (byte) ram ( 4 bits) instruction cycle cmos input cmos input/ output cmos output 20 ? led direct drive capability : 8 ? mask option pull-down resistor incorporation capability : 4 5 ? pwm/pulse output : 1 ? led direct drive capability : 4 ? mask option pull-down resistor incorporation capability : 4 26 ? 40 v max. ? pull-down resistor incorporation or open-drain output specifiable by mask option i/o ports fip? dual-func- tion pin included and fip dedicated pin excluded fip controller/ driver high-voltage output no. of segments no. of digits timer serial interface C40 to +85 c C10 to +70 c C40 to +70 c 2.7 to 6.0 v 5v 10 % 2.7 to 6.0 v ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp(14 20 mm) ? 64-pin ceramic wqfn (14 20 mm) ? 64-pin plastic shrink dip (750 mil) www.datasheet.co.kr datasheet pdf - http://www..net/ 68 m pd75216a * can be operated at 6.0 mhz. if used in 16k mode, can be used for evaluation and limited production of the m pd75216a series. www.datasheet.co.kr datasheet pdf - http://www..net/ 69 m pd75216a appendix b. development tools the following development tools are available for the development of systems using the m pd75216a. ie-75000-r *1 in-circuit emulator for the 75x series ie-75001-r ie-75000-r-em *2 emulation board for the ie-75000-r and ie-75001-r ep-75216acw-r emulation probe for m pD75216ACW ep-75216agf-r emulation probe for m pd75216agf the 64-pin conversion socket ev-9200g-64 ev-9200g-64 pg-1500 prom programmer pa-75p216acw prom programmer adapter for m pd75p216acw/75p218cw in connection with pg-1500 pa-75p218gf prom programmer adapter for m pd75p218gf in connection with pg-1500 pa-75p218kb prom programmer adapter for m pd75p218kb in connection with pg-1500. ie control program host machine pg-1500 controller ? pc-9800 series (ms-dos? ver.3.30 to ver.5.00a *3 ) ra75x relocatable assembler ? ibm pc/at? (pc dos? ver.3.1) *1. maintenance product 2. not incorporated in the ie-75001-r 3. the task swap function, which is provided with ver.5.00/5.00a, is not available with this software. remarks for development tools manufactured by a third party, see the 75x series selection guide (if-151) . software hardware h www.datasheet.co.kr datasheet pdf - http://www..net/ 70 m pd75216a appendix c. related documents device related documents document name document no. users manual instruction application table application note 75x series selection guide development tools related documents document name document no. ie-75000-r/ie-75001-r users manual ie-75000-r-em users manual ep-75216acw-r users manual ep-75216agf-r users manual pg-1500 users manual ra75x assembler package users manual operation volume language volume pg-1500 controller users manual other documents document name document no. package manual surface mount technology manual quality grade on nec semiconductor devices nec semiconductor device reliability & quality control electrostatic discharge (esd) test semiconductor devices quality guarantee guide microcomputer related products guide other manufactures volume note the contents of the above related documents are subjected to change without notice. the latest documents should be used for design, etc. hardware software www.datasheet.co.kr datasheet pdf - http://www..net/ 71 m pd75216a www.datasheet.co.kr datasheet pdf - http://www..net/ [memo] [memo] m pd75216a no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. m4 92.6 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. eeprom is a trademark of nec corporation. fip is a trademark of nec corporation. ms-dos is a trademark of microsoft corporation. pc dos, pc/at are trademarks of ibm corporation. www.datasheet.co.kr datasheet pdf - http://www..net/ |
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